In an integrated circuit (IC) chip design flow, logic synthesis is a stage that creates a gate-level netlist of an IC chip design, and placement and routing is a stage that creates a design layout corresponding to the gate-level netlist. During logic synthesis, logic gates and registers in the gate-level netlist are mapped to predetermined standard cells in a library. During placement, locations of the mapped standard cells in the design layout are determined. During routing, router-routed interconnects connecting the placed standard cells in the design layout are created.